Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

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The multiplier A and the multiplicand B can be represented as. As the nano devices are developed, the density of digital chips is being increased naturally seeking the solution for the power consumption and the heat dissipation developed by this power consumption.

Other constraint in designing reversible logic circuit is optimizing garbage outputs. Block diagram of 4-bit Baugh-Wooly multiplier. These reversible multiplier cells are targeted for reversible Baugh-Wooley multiplier design. Efficient realization of large size two’s complement multipliers using embedded blocks in FPGAs.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog – Semantic Scholar

The Toffoli gate synthesis of the proposed reversible multiplier cell is also given. Out of the five outputs, two outputs Q and R are left unspecified, since these are the garbage outputs.


The input D is the sum input from the previous cells. By clicking multoplier or continuing to use the site, you agree to the terms outlined in our Privacy PolicyTerms of Serviceand Dataset License. The representation has the Gate Count of Discrete cosine transform Carry-select adder Performance Evaluation Digital data. This work also involves two steps as in [5]. This paper provides the design of compact Baugh-Wooley multiplier using reversible multiplief.

References Publications referenced by this paper.

International Mulltiplier of Theoretical Physics, 21, Therefore, the hardware intricacy of the proposed design is less compared to the existing approaches. The outputs P, Q and R are considered as garbage outputs. Also the relationship between the inputs and outputs should be maintained as one-to-one and unique. International Journal on Engineering Science multippier Technology, 2, Since the proposed cells are incompletely specified cells we could not generate the Quantum cost and therefore we could not evaluate the proposed gates based on the Quantum cost.

Let the numbers to be multiplied be A and B.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

One of the major factors in the design of a reversible logic circuit is the number of constant inputs. The conclusion multipoier the above discussion is that, it is evident that the proposed reversible Baugh-Wooley multiplier circuit design is better than the existing designs with respect to gate counts, garbage inputs and garbage outputs.


Hence the proposed Baugh- Wooley Multiplier design is better than existing designs. Comparison of proposed and existing design. The block diagram representation of 4 bit Baugh-Wooley multiplier is shown in Figure 5. This can be understood easily with the help of the comparison results shown in Table 1.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

World Applied Sciences Journal, 10, Truncated multiplication with multipleir rounding E. World Applied Sciences Journal, 3, Data-dependent truncation scheme for parallel multipliers E KingE.

Therefore the proposed multiplier cells are evaluated based on the Gate count, Garbage inputs and Garbage outputs. It has been done in two steps as follows: The organization of the paper is as follows.